The steady increase in the complexity and clock rate of integrated circuits requires shorter interconnection paths and closer packing of integrated circuit chips. The close packing of integrated circuits is measured by the packaging efficiency, the area required for a single integrated circuit chip and its interconnections.
Flip chip or C4 (Controlled Collapse Chip Connection) has about 90% packaging efficiency for a 10 mm.times.10 mm die. Wire bonding and TAB (Tape Automated Bonding) have packaging efficiencies of about 75% and 50%, respectively, for the same size die.
The C4 process has high packaging efficiency because the connections from the chip to the first level package are underneath the chip, and the connections from the first level package to the second level package are in an area array also underneath the chip. Wire bond and TAB interconnections to the first level package fan out from the periphery of the chip decreasing the packaging efficiency.
The C4 process has been used by only a few large volume manufacturers because it requires specially designed integrated circuits. The contacts of integrated circuits for the C4 process are in a grid over the surface of the chip, not on the perimeter as in the usual integrated circuit. Also the chips must be specially prepared for the user by the integrated circuit manufacturer with a thin layer of chromium and 0.1 mm (4 mil) high bumps of 97 Pb/3 Sn solder over the contacts.
Thick film hybrids have seen limited use as packages for the C4 process. Conventional, thick film, hybrid circuits are produced by screen printing. Minimum conductor widths are 125 .mu.m (0.005"), minimum spacing between the conductors is 125 .mu.m and the vias or openings between conductive pattern layers are typically 300 .mu.m (0.012"). The theoretical line density or connectivity of thick film, hybrid circuits is 30 cm/cm.sup.2 (75 in/in.sup.2. The actual connectivity is 50% of the theoretical or 15 cm/cm.sup.2. That means too many conductor layers are needed when interconnecting high pin count devices, and so conventional hybrid circuits can not readily provide high packaging efficiency.
Miniature flexible circuits have been designed to provide packaging efficiencies similar to the C4 process. The flexible circuits can be used with conventional integrated circuits having perimeter contacts. Gold conductors of the flexible circuit are thermosonically bonded the integrated circuits contacts. The conductors of the flexible circuit don't fan out from the integrated circuit contacts into the area around the chip, instead the conductors fan in underneath the chip terminating in a grid array of metal bumps underneath the chip for interconnection to second level packaging. The flexible circuit is bonded to the chip with an elastomeric adhesive 0.15 mm (6 mil) thick. The elastomeric adhesive and the flexible circuit materials limit the temperature range in manufacture and use, make the electrical properties sensitive to moisture, and prevent its use in hermetically sealed packages.
For new designs, the yield of good integrated circuits from a wafer is in the range of 10-35%. To increase the percentage of good integrated circuits in a batch, the circuits are tested in wafer form before cutting the dice out of the wafer. The power supply currents (DC testing) may be tested or the wafers may be boundary scan tested according to IEEE Standard 1149.1. Boundary scan testing of a wafer determines whether the gates of an individual circuit are functional, but it does not determine if the gates switch at the required speed, and does not check the integrity of the connections to the input/output pads (IOs) of the circuit. About 10% of the dice which pass the boundary scan test at the wafer level fail when mounted in a first level package and tested at speed and for functional parameters. In any multichip module (MCM) that contains several chips, the yield of good circuits from final assembly drops dramatically with die reliability. Even if the dice had been boundary scan tested in wafer form (90% good dice) only 35% of MCMs containing eight dice will be good after final assembly.
Testing the chips before final assembly to obtain known good die (KGD) greatly reduces the rework and the associated costs. Most dice are packaged, since the package enables testing to obtain KGD. However, the package takes up 2 to 10 times the area of the chip lowering the packaging efficiency and compromising the circuit performance. Although some temporary packages have been proposed for testing bare dice to obtain KGD, they have not yet found wide acceptance.